The present invention pertains to the field of level conversion circuit technology; in particular, it pertains to a bidirectional level conversion circuit.
The integration density of ICs for electronic equipment systems is increasing, with corresponding reductions in the power supply voltages used. For example, with the advent of LSI, a system which formerly operated with a 5V power supply came to require only a low-voltage power supply, such as 3.3V or 2.5V. Furthermore, in recent years, it has become more common with ICs to use several power supply voltages. With such a system, it is necessary to apply a level conversion to a 5V signal to obtain a low-voltage signal of 3.3V, or to apply level conversion to a low-voltage signal of 3.3V to obtain 5V, for example.
This type of conversion can be achieved using a variety of methods, and special logic ICs for level conversion are also available.
Reference numeral 101 in FIG. 3 indicates an example level conversion circuit which uses a pass transistor 102 from an N-channel MOS transistor out of the internal circuit of a logic IC of the prior art.
In said level conversion circuit 101, the gate terminal of pass transistor 102 is connected to power supply voltage line C via diode 103, and pass transistor 102 is turned on by power supply voltage VCC from power supply voltage line C. When the voltage at the gate terminal with respect to the source terminal is denoted as gate voltage Vtn, voltage VB at port B serving as the source terminal will be lower than voltage Vs0 of the gate terminal by gate voltage (threshold voltage) Vtn regardless of the level of voltage VA at port A serving as a drain terminal.
That is, voltage VB at port B is restricted to (voltage VS0 of gate terminalxe2x88x92gate voltage Vtn) as long as voltage VA of port A is higher than voltage VB of port B.
For example, as long as the voltage of port terminal A is 3.3V or higher, a voltage VB=3.3V can be generated by level-converting voltage VA at port A if Vtn=1.0V, and voltage VS0 at gate terminal is 4.3V to give an output of 3.3V voltage at port B. Therefore, even if voltages of 5V and 3.3V must both be handled in terms of interfacing with the bus, both voltages can be handled by keeping pass transistor 102 conductive.
Also, because the propagation of a signal from port A to port B can be shut off by bringing voltage VS0 of the gate terminal to the GND level and disconnecting pass transistor 102, hot-line attachment/detachment function of the bus can be realized effectively. The delay time of a signal from port A to port B can be made small enough to be ignored by reducing the on-resistance of pass transistor 102.
While the level conversion circuit 101 is capable of high level to low level conversion, it is incapable of low level to high level conversion. When it is used for interfacing with a bus, there are many cases which require bidirectional level conversion.
Reference numeral 111 in FIG. 4 shows an example of such a level conversion circuit, where the configuration is identical to that of level conversion circuit 101 in FIG. 3, except that port A is pulled up to the level of high voltage power supply terminal D with pull-up resistor 115.
Here, too, in the case of said level conversion circuit 111, assuming that the voltage on the gate terminal of pass transistor 102 is VS0, pass transistor 102 turns off if voltage VB at port B is greater than or equal to VS0xe2x88x92Vtn. As a result, high power supply voltage VCCH is applied at port A via pull-up resistor 115. If high power supply voltage VCCH is 5.0V, and voltage VB at port B is 3.3V, voltage VA at port A is 5.0V, which means that the low voltage signal of 3.3V has been level-converted to a high voltage signal of 5.0V.
Although capable of bidirectional level conversion between ports A and B, said level conversion circuit 111 has the following shortcomings.
(1) When voltage VA at port A changes from low level to high level as voltage VB at port B is propagated to port A, said change in voltage is regulated in accordance with a time constant determined on the basis of the resistance of pull-up resistor 115 and the load capacitance of port A at the point where the level of voltage VA has become greater than VS0xe2x88x92Vtn, so that the change is subject to a delay. Therefore, the circuit cannot follow high-frequency signals.
(2) When voltage VA at port A is at the low level, there is a continuous large current flow into pull-up resistor 115.
(3) Because pull-up resistor 115 is outside to level conversion circuit 111, that is, an extra part is needed, extra real estate is required.
A general object of the present invention is to present a power-saving and space-saving level conversion circuit capable of bidirectional level conversion even for high-frequency signals.
In order to solve the problems, the level conversion circuit of one aspect of the present invention is provided with a first port to which a first logic level signal is applied, a second port to which a second logic level signal is applied, which has a logic level lower than the first logic level, a transistor connected between the first and the second ports, a first switching circuit which is connected between a power supply terminal to which a power supply voltage corresponding to the first logic level is applied and the first port and becomes conductive according to the first port level, and a second switching circuit which is connected between the power supply terminal to which the power supply voltage corresponding to the first logic level is applied and the first port and becomes conductive together with the first switching circuit only for a prescribed period, wherein a signal having different levels can be propagated from the first port to the second port or from the second port to the first port.
In one aspect of the present invention, it is desirable that the resistance be greater when the first switching circuit is conductive than when the second switching circuit is conductive. Preferably, it is provided with a pulse generator which generates a pulse signal used for temporarily turning on the second switching circuit in accordance with changes in the logic level of the first port.
In addition, in one aspect of the present invention, it is desirable that the pass transistor and the first and the second switching circuits be configured with MOS transistors. Preferably, in accordance with an aspect of the present invention, the transistor is an NMOS transistor, and a voltage higher than a power supply voltage corresponding to the second logic level by an amount equivalent to the threshold voltage of said NMOS transistor is applied to the gate terminal of the NMOS transistor.
Furthermore, it is desirable, according to another aspect of the invention, that it be provided with a NAND gate having 2 input terminals respectively connected to the first port and an enable signal application terminal and a power supply circuit configured with a diode and a resistor connected in series between the power supply terminal to which the power supply voltage corresponding to the first logic level is supplied and a power supply terminal to which a reference voltage is supplied, where the first and the second switching circuits are respectively configured with first and second PMOS transistors, the first pulse generator is configured with a resistor and a capacitor connected in series between the power supply terminal to which the power supply voltage corresponding to the first logic level is supplied and the output terminal of the NAND gate, and the gate terminal of the first PMOS transistor is connected to the output terminal of the NAND gate, the gate terminal of the second PMOS transistor is connected to the midpoint of the connection node between the resistor and the capacitor of the pulse generator, the gate terminal of the NMOS transistor is connected to the midpoint of the connection node between the diode and the resistor of the voltage supplying circuit.
According to a further aspect of the present invention, when a low-level signal is referenced to ground potential, the power supply voltages corresponding to the first and second logic levels are at positive or negative voltages, and the first and the second ports serve as a transmission path for a binary signal comprising high and low levels with different logic levels.
A transistor is provided according to an aspect of the invention between the first and the second ports, where the terminals are disconnected from each other when the transistor is turned off and connected when it is turned on.,
When, in accordance with an aspect of the invention, the transistor is a MOS transistor and is configured so that the source terminal is connected to the second port on the low voltage side, the drain is connected to the first port on the high voltage side, and a voltage greater than or equal to the threshold voltage is applied to the gate terminal with respect to the source terminal, the drain terminal voltage changes according to the source terminal voltage, so that when a signal having the second logic level is applied to the source terminal, a signal having a higher logic level, that is, the first logic level, can be obtained at the drain terminal.
When, in accordance with an aspect of the invention, the potential of the second port is to be changed from the reference potential to the power supply voltage corresponding to the second logic level, the potential of the power supply voltage supplied to the first and the second switching circuits is changed to that of the power supply voltage corresponding to the first logic level. In this case, if the second switching circuit conducts when the potential of the first port begins to change, a large current is supplied to the first port from the power supply. Thus, the load capacitor connected to the first port gets charged quickly, and a waveform of a quickly changing voltage can be obtained.
On the other hand, when, in accordance with an aspect of the invention, changing the potential of the first port from that of the power supply voltage corresponding to the first logic level to the reference potential by changing the potential of the second port from the power supply voltage corresponding to the second logic level to the reference potential, the second switching circuit is kept on in order to reduce the burden on the circuit for changing the potential of the second port.